1. Field of the Invention
The present invention relates to a semiconductor device and particularly to an improvement of a programming high-voltage pulse generator in an electrically erasable programmable read-only memory of a 5 V single power source, i.e., 5 V-only EEPROM.
2. Description of the Prior Art
FIG. 1 is a schematic diagram showing a structure of a conventional programming high-voltage generator, as disclosed for example in "High-Voltage Regulation and Process Considerations for High-Density 5 V-only E.sup.2 PROM's" by Duane H. Oto et al., IEEE Journal of Solid-State Circuits, Vol. SC-18, No. 5 (1983), pp. 532-538. Referring to FIG. 1, the structure and the operation of the conventional circuit for generating a programming high-voltage pulse V.sub.pp will be described in the following.
This circuit comprises as a reference signal generating system: a reference voltage generator 1 for generating a reference voltage signal V.sub.ref for controlling the height of a programming high-voltage pulse V.sub.pp and supplying the reference voltage signal V.sub.ref to an RC network 5; an oscillator 2 for supplying two clock pulses nonoverlapping with each other to the respective gate electrodes of the MOS transistors 9 and 10 included in the RC network 5 so that the time constant of the RC network 5 is controlled; the RC network 5 for making gentle (or dull) the rise of the reference voltage signal V.sub.ref from the reference voltage generator 1 in response to the signal frequency from the oscillator 2 and providing the signal V.sub.ref to a node A; a timer 3 for generating a pulse signal for controlling the pulse width of the high-voltage pulse V.sub.pp ; and a switching MOS transistor 4 turning on and off in response to the signal from the timer 3 so as to control the potential at the node A.
The above stated RC network 5 comprises a switched-capacitor 6 and a capacitor 7. The switched-capacitor 6 comprises MOS transistors 9 and 10 turning on and off alternately by receiving at the gate electrodes thereof the two phase nonoverlapping clock signals from the oscillator 2 and also comprises a capacitor 11 having one electrode connected to a junction of the MOS transistors 9 and 10 and the other electrode grounded. The capacitors 7 and 11 each are structured by an oxide film formed by the same manufacturing process as for the gate oxide film of a MOS transistor.
Further, the circuit shown in FIG. 1 comprises as a signal amplifying system: a comparator 12 for receiving and comparing the potential at the node A and the level of a signal from a voltage divider 14 to provide an activation signal to a driver 15 if the potential at the node A is higher than the signal level from the voltage divider 14; a charge pump 13 operative in response to the activation signal from the driver 15 to multiply the voltage so as to provide a programming high-voltage pulse V.sub.pp to a memory transistor (not shown) of the EEPROM and to the voltage divider 14; and the voltage divider 14 for dividing the voltage signal received from the charge pump 13 by a predetermined division ratio and providing the result of the division to the comparator 12.
FIG. 2 is a diagram showing a waveform of the programming high-voltage pulse V.sub.pp. The height h of the pulse V.sub.pp is controlled by the signal from the reference voltage generator 1; a rise time .tau. is controlled by the RC network 5; and a pulse width w is controlled by a signal from the timer 3.
Now, referring to FIGS. 1 and 2, the operation of the programming high-voltage generating circuit will be described.
When the signal supplied from the timer 3 to the MOS transistor 4 reaches the level "L", the MOS transistor 4 is brought into the OFF-state. On the other hand, the MOS transistors 9 and 10 turn on and off alternately in response to the clock signal from the oscillator 2. As a result, the output reference voltage V.sub.ref from the reference voltage generator 1 is transmitted to the node A through the RC network 5. The RC network 5 comprises the switched-capacitor 6 and the capacitor 7. The resistance value of the switched-capacitor 6 is controlled by the frequency of the clock signal from the oscillator 2 and by the ratio of the capacitance 7 and 11. Accordingly, in response to the turning-off of the MOS transistor 4, a signal having a gentle rise according to the time constant .tau. defined by the frequency of the signal from the oscillator 2 is supplied to the node A. The potential at the node A serves as an input of the comparator 12, where it is compared with the output voltage V.sub.pp from the charge pump 13 divided by the voltage divider 14. The output of the comparator 12 is supplied to the driver 15 for driving the charge pump 13. The comparator 12 generates a signal for activating the driver 15 when the potential at the node A is higher than the signal level from the voltage divider 14. Consequently, the voltage obtained by dividing the voltage at the node A by a division ratio of the voltage divider 14 becomes an output of the charge pump 13, that is, the programming high-voltage pulse V.sub.pp.
Then, when the output of the timer 3 attains the level "H", the MOS transistor 4 is brought into the ON-state. Accordingly, the potential at the node A becomes a ground potential through the conducting MOS transistor 4, and as a result, the generation of the programming high-voltage pulse V.sub.pp from the charge pump 13 is stopped since the comparator 12 does not supply the activating signal to the drive circuit 15.
The potential at the node A rises to the level of the reference voltage signal V.sub.ref with the time constant .tau. of the RC network 5 in response to the turn-off of the MOS transistor 4. Consequently, the output pulse V.sub.pp from the charge pump 13 also rises with the time constant .tau.. The height h of the pulse signal V.sub.pp is equal to a value obtained by dividing the reference voltage V.sub.ref by the division ratio of the voltage divider 14 and the pulse width w of the pulse signal V.sub.pp is determined by the output signal from the timer 3. The rise of the pulse V.sub.pp is made gentle by using the RC network 5 so that too high an electric field may not be applied to the tunnel oxide film (21 in FIG. 3) of the memory transistor of the EEPROM. Typically, the rise time constant .tau. is set to be 600 .mu.sec.
FIG. 3 is a sectional view showing schematically a structure of a memory transistor of an EEPROM. In FIG. 3, the memory transistor comprises: a semiconductor substrate 20; a drain 18 and a source 19 formed at the surface of the semiconductor substrate 20; a floating gate 17 formed on the semiconductor substrate 20 through a first insulating layer to store electric charges; and a control gate 16 formed on the floating gate 17 through a second insulating layer for controlling the charge and discharge of the floating gate 17. In the following, the first insulating layer serving as a path for electric charges between the drain region 18 and the floating gate 17 is referred to as a tunnel oxide film 21, and the second insulating layer between the floating gate 17 and the control gate 16 is referred to as a polysilicon-polysilicon interlayer oxide film 23. V.sub.G, V.sub.D, and V.sub.S indicate the voltage supplied to the control gate 16, the drain 18 and the source 19, respectively.
Now, the programming operation of the EEPROM will be described. The programming operation comprises an erasing mode and a writing mode. First, the operation in the erasing mode will be described.
In the erasing mode, the high-voltage pulse V.sub.pp from the programming high-voltage generator shown in FIG. 1 is supplied to the control gate 16 (V.sub.g =V.sub.pp in FIG. 3) while the source region 19, the drain region 18 and the substrate 20 are grounded (V.sub.S =V.sub.D =0 in FIG. 3). At this time, a tunnel current flows between the drain region 18 and the floating gate 17 through the tunnel oxide film 21 and electrons are injected into the floating gate 17, so that the threshold voltage of the memory transistor is increased.
In the writing mode, the high-voltage pulse signal V.sub.pp from the high-voltage generator is applied to the drain 18 (V.sub.D =V.sub.pp in FIG. 3), the source region 19 is held in an electrically floating state and the control gate 16 and the semiconductor substrate 20 are grounded (V.sub.G =0 in FIG. 3). Thus, electrons flow out of the floating gate 17 through the tunnel oxide film 21 so that positive charges are stored in the floating gate 17. As a result, the threshold voltage of the memory transistor is lowered. The electric field applied to the tunnel oxide film 21 for controlling a shift amount of the threshold voltage is determined by a ratio of a capacitance between the control gate 16 and the floating gate 17 and a capacitance between the floating gate 17 and the drain 18. When the thickness of the polysilicon-polysilicon interlayer oxide film 23 and the thickness of the tunnel oxide film 21 are changed, the intensity of the electric field applied to the tunnel oxide film 21 changes even if the same voltage is applied to the control gate 16 in the erasing mode for example. Therefore, even if the same programming high-voltage pulse signal V.sub.pp is applied to the control gate 16, the shift amount .DELTA.Vth of the threshold voltage of the memory transistor of the EEPROM changes in case where the thicknesses of these oxide films varies.
FIGS. 4 and 5 are graphs showing the results obtained by simulation concerning a change in a threshold voltage shift amount .DELTA.Vth in case where the thicknesses of the oxide films varies in the erasing mode. Although the following description concerns only the erasing mode for ocnvenience sake, it is the same with the writing mode.
FIG. 4 is a graph showing a threshold voltage shift amount .DELTA.Vth obtained by simulation in case where the thickness of the tunnel oxide film 21 varies in a range of 80 .ANG. to 100 .ANG. with the thickness of the polysilicon-polysilicon oxide film 23 being maintained 800 .ANG.. In FIG. 4, the horizontal axis represents a pulse width of the programming high-voltage pulse V.sub.pp and the vertical axis represents a threshold voltage shift amount .DELTA.Vth. As is clear from FIG. 4, in case where the pulse width of the high-voltage pulse V.sub.pp is 2 milliseconds with the potential of the pulse V.sub.pp being 21 V and the rise time constant .tau. of the pulse V.sub.pp being 0.6 millisecond, the threshold voltage shift amount .DELTA.Vth changes in a range of 1.9 V to 4.5 V according to the thickness of the tunnel oxide film.
FIG. 5 is a graph showing a threshold voltage shift amount .DELTA.Vth obtained by simulation in case where the thickness of the polysilicon-polysilicon interlayer oxide film 23 is changed in a range of 700 .ANG. to 900 .ANG. with the thickness of the tunnel oxide film being maintained 90 .ANG.. In FIG. 5, the horizontal axis represents a pulse width of the pulse V.sub.pp and the vertical axis represents a threshold value shift amount .DELTA.Vth. The potential (height) of the pulse V.sub.pp is 24 V and the rise time constant .tau. of the RC network 5 is 1 millisecond. In this case also, in the same manner as in FIG. 4, it can be seen that the threshold voltage shift amount .DELTA.Vth largely changes according to the change of the thickness of the polysilicon-polysilicon interlayer oxide film.
Therefore, if the thicknesses of the oxide films are varied, it is necessary to change the waveform of the high-voltage pulse V.sub.pp according to the thicknesses of the oxide films so as to obtain a constant threshold voltage shift amount .DELTA.Vth. This is because the change of the threshold voltage is caused by the flowing-in and flowing-out of electric charges in the floating gate and the flowing-in and flowing-out amount of electric charges is defined by the height h and the pulse width w of the high-voltage pulse V.sub.pp and the rise time constant .tau. of the RC network.
It is important to make the threshold voltage shift amount .DELTA.Vth constant for the purpose of securing the reliability of the EEPROM and a stable operation for reading and retaining the stored data in the EEPROM.
Conventionally, as described in the above stated prior art reference, control is made by a program to change the level of the output signal V.sub.ref of the reference voltage generator for each chip according to the thicknesses of the oxide films. However, the above described conventional method involves problems that the time required for a function test of an EEPROM is long and a programming device for controlling the output of the reference voltage generator needs to be provided.